----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:58:45 11/20/2011 
-- Design Name: 
-- Module Name:    nextpc - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.global_definition.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity nextpc is
	port (
			NEXT_PC : out STD_ULOGIC_VECTOR(15 downto 0);
			
			PC		: in   STD_ULOGIC_VECTOR(15 downto 0);
			PC_B	: in   STD_ULOGIC_VECTOR(15 downto 0);
			Reg1	: in   STD_ULOGIC_VECTOR(15 downto 0);
			OP		: in   STD_ULOGIC_VECTOR(5 downto 0)
		 );
end nextpc;

architecture Behavioral of nextpc is
begin
	process(OP, PC, PC_B, Reg1)
	begin
		case OP is
			when OP_B =>
				NEXT_PC <= PC_B;
			when OP_BEQZ | OP_BTEQZ =>
				if (Reg1 = x"0000") then
					NEXT_PC <= PC_B;
				else
					NEXT_PC <= PC;
				end if;
			when OP_BNEZ | OP_BTNEZ =>
				if (Reg1 = x"0000") then
					NEXT_PC <= PC;
				else
					NEXT_PC <= PC_B;
				end if;
			when OP_JALR | OP_JR | OP_JRRA =>
				NEXT_PC <= Reg1;
			when OP_INT3 =>
				NEXT_PC <= Reg1 and x"7FFF";
			when others =>
				NEXT_PC <= PC;
		end case;
	end process;
end Behavioral;

